部分　引言 章　基本概念和計(jì)算機(jī)演化1 1.1　組成與體系結(jié)構(gòu)2 1.2　結(jié)構(gòu)與功能3 1.3　計(jì)算機(jī)簡(jiǎn)史11 1.4　Intel x86體系結(jié)構(gòu)的演化27 1.5　嵌入式系統(tǒng)29 1.6　ARM體系結(jié)構(gòu)33 1.7　云計(jì)算39 1.8　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題42 2章　性能問(wèn)題45 2.1　優(yōu)化性能設(shè)計(jì)46 2.2　多核、MIC和GPGPU52 2.3　深刻理解性能的兩個(gè)定律：A*dahl定律和Little定律53 2.4　計(jì)算機(jī)性能的基本度量56 2.5　計(jì)算均值59 2.6　基準(zhǔn)測(cè)試和SPEC67 2.7　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題74 二部分　計(jì)算機(jī)系統(tǒng) 3章　計(jì)算機(jī)功能與互連的頂層視圖80 3.1　計(jì)算機(jī)組件81 3.2　計(jì)算機(jī)功能83 3.3　互連結(jié)構(gòu)99 3.4　總線互連0 3.5　點(diǎn)對(duì)點(diǎn)互連2 3.6　PCI Express7 3.7　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題116 4章　高速緩存120 4.1　計(jì)算機(jī)存儲(chǔ)系統(tǒng)概述121 4.2　高速緩存存儲(chǔ)器原理128 4.3　高速緩存設(shè)計(jì)要素131 4.4　Pentium 4 高速緩存結(jié)構(gòu)149 4.5　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題152 附錄4A　兩級(jí)存儲(chǔ)的性能特征157 5章　內(nèi)部存儲(chǔ)器165 5.1　半導(dǎo)體主存166 5.2　糾錯(cuò)174 5.3　DDR DRAM180 5.4　閃存185 5.5　新的易失性固態(tài)存儲(chǔ)器技術(shù)187 5.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題190 6章　外部存儲(chǔ)器194 6.1　磁盤195 6.2　RAID204 6.3　固態(tài)硬盤212 6.4　光學(xué)存儲(chǔ)器217 6.5　磁帶222 6.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題224 7章　輸入/輸出228 7.1　外部設(shè)備230 7.2　I/O模塊232 7.3　可編程I/O235 7.4　中斷驅(qū)動(dòng)的I/O239 7.5　直接存儲(chǔ)器訪問(wèn)248 7.6　直接高速緩存訪問(wèn)254 7.7　I/O通道和處理器261 7.8　外部互連標(biāo)準(zhǔn)263 7.9　IBM zEnterprise EC12 I/O系統(tǒng)266 7.　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題270 8章　作系統(tǒng)支持275 8.1　作系統(tǒng)概述276 8.2　調(diào)度287 8.3　存儲(chǔ)管理293 8.4　Intel x86存儲(chǔ)管理304 8.5　ARM存儲(chǔ)管理309 8.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題314 三部分　算術(shù)與邏輯 9章　數(shù)字系統(tǒng)318 9.1　十進(jìn)制系統(tǒng)319 9.2　按位記數(shù)系統(tǒng)320 9.3　二進(jìn)制系統(tǒng)321 9.4　二進(jìn)制與十進(jìn)制的轉(zhuǎn)換321 9.5　十六進(jìn)制表示324 9.6　關(guān)鍵詞和練習(xí)題326 0章　計(jì)算機(jī)算術(shù)運(yùn)算328 .1　算術(shù)與邏輯單元329 .2　整數(shù)表示330 .3　整數(shù)算術(shù)運(yùn)算335 .4　浮點(diǎn)表示350 .5　浮點(diǎn)算術(shù)運(yùn)算358 .6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題367 1章　數(shù)字邏輯372 11.1　布爾代數(shù)373 11.2　門376 11.3　組合電路378 11.4　時(shí)序電路396 11.5　可編程邏輯設(shè)備405 11.6　關(guān)鍵詞和練習(xí)題409 四部分　中央處理單元 2章　指令集：特點(diǎn)與功能412 12.1　機(jī)器指令特點(diǎn)413 12.2　作數(shù)類型420 12.3　Intel x86和ARM的數(shù)據(jù)類型422 12.4　作類型425 12.5　Intel x86和ARM的作類型438 12.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題446 附錄12A　小端序、大端序和雙端序452 3章　指令集：尋址模式與格式456 13.1　尋址模式457 13.2　x86和ARM的尋址模式463 13.3　指令格式469 13.4　x86和ARM指令格式477 13.5　匯編語(yǔ)言482 13.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題484 4章　處理器結(jié)構(gòu)與功能488 14.1　處理器組成489 14.2　寄存器組成491 14.3　指令周期496 14.4　指令流*線500 14.5　x86處理器系列517 14.6　ARM處理器524 14.7　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題530 5章　精簡(jiǎn)指令集計(jì)算機(jī)535 15.1　指令執(zhí)行特性537 15.2　大寄存器文件的使用542 15.3　基于編譯器的寄存器優(yōu)化547 15.4　精簡(jiǎn)指令集架構(gòu)549 15.5　RISC流*線555 15.6　MIPS R4000559 15.7　SPARC565 15.8　RISC與CISC之爭(zhēng)570 15.9　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題571 6章　指令級(jí)并行與超標(biāo)量處理器575 16.1　概述576 16.2　設(shè)計(jì)問(wèn)題581 16.3　 Intel Core微架構(gòu)591 16.4　ARM Cortex-A8596 16.5　ARM Cortex-M3604 16.6　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題608 五部分　并行結(jié)構(gòu) 7章　并行處理613 17.1　多處理器結(jié)構(gòu)615 17.2　對(duì)稱多處理器617 17.3　高速緩存一致性和MESI協(xié)議621 17.4　多線程和*上多處理器628 17.5　集*633 17.6　均勻內(nèi)存訪問(wèn)640 17.7　云計(jì)算643 17.8　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題650 8章　多核計(jì)算機(jī)656 18.1　硬件性能問(wèn)題657 18.2　軟件性能問(wèn)題660 18.3　多核結(jié)構(gòu)665 18.4　異構(gòu)多核結(jié)構(gòu)667 18.5　Intel Core i7-990X676 18.6　ARM Cortex-A15 MPCore677 18.7　IBM zEnterprise EC12機(jī)682 18.8　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題685 9章　通用圖形處理單元688 19.1　CUDA基礎(chǔ)689 19.2　GPU與CPU691 19.3　GPU架構(gòu)概述692 19.4　Intel的Gen8 GPU701 19.5　何時(shí)把GPU當(dāng)作協(xié)處理器使用704 19.6　關(guān)鍵詞和復(fù)習(xí)題706 六部分　控制單元 20章　控制單元作707 20.1　微作708 20.2　處理器的控制714 20.3　硬布線實(shí)現(xiàn)724 20.4　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題727 21章　微程序控制729 21.1　基本概念730 21.2　微指令序列739 21.3　微指令執(zhí)行745 21.4　TI 8800755 21.5　關(guān)鍵詞、復(fù)習(xí)題和練習(xí)題766 附錄A　計(jì)算機(jī)組成與體系結(jié)構(gòu)教學(xué)項(xiàng)目768 附錄B　匯編語(yǔ)言與相關(guān)主題774 參考文獻(xiàn)800 Contents Foreword ii Preface xv About the Author xii PART ONE INTRODUCTION 1 Chapter.1 Basic Concepts and Computer Evolution 1 1.1 Organiz*ion and Archite*ure 2 1.2 Stru*ure and Fun*ion 3 1.3 A Brief History of Compute* 11 1.4 The Evolution of the Intel x86 Archite*ure 27 1.5 Embedded Systems 29 1.6 Arm Archite*ure 33 1.7 Cloud Computing 39 1.8 Key Terms, Review Questions, and Problems 42 Chapter.2 Perfor*nce Issues 45 2.1 Designing for Perfor*nce 46 2.2 Multicore, Mics, and GPGPUs 52 2.3 Two Laws th* Provide Insight:A*dahl’s Law and Little’s Law 53 2.4 Basic Measures of Computer Perfor*nce 56 2.5 Calcul*ing the Mean 59 2.6 Bench*rks and Spec 67 2.7 Key Terms, Review Questions, and Problems 74 PART TWO THE PUTER SYSTEM 80 Chapter.3 A Top-Level View of Computer Fun*ion and Interconne*ion 80 3.1 Computer Components 81 3.2 Computer Fun*ion 83 3.3 Interconne*ion Stru*ures 99 3.4 Bus Interconne*ion 0 3.5 Point-to-Point Interconne* 2 3.6 PCI Express 7 3.7 Key Terms, Review Questions, and Problems 116 Chapter.4 Cache Memory 120 4.1 Computer Memory System Overview 121 4.2 Cache Memory Principles 128 4.3 Elements of Cache Design 131 4.4 Pentium 4 Cache Organiz*ion 149 4.5 Key Terms, Review Questions, and Problems 152 Appendix 4A Perfor*nce Chara*eristics of Two-Level Memories 157 Chapter.5 Internal Memory 165 5.1 Semicondu*or Main Memory 166 5.2 Error Corre*ion 174 5.3 DDR DRAM 180 5.4 Flash Memory 185 5.5 Newer Nonvol*ile Solid-St*e Memory Techogies 187 5.6 Key Terms, Review Questions, and Problems 190 Chapter.6 External Memory 194 6.1 Magic Disk 195 6.2 RAID 204 6.3 Solid St*e Drives 212 6.4 Optical Memory 217 6.5 Magic Tape 222 6.6 Key Terms, Review Questions, and Problems 224 Chapter.7 Input/Output 228 7.1 External Devices 230 7.2 I/O Modules 232 7.3 Programmed I/O 235 7.4 Interrupt-Driven I/O 239 7.5 Dire* Memory Access 248 7.6 Dire* Cache Access 254 7.7 I/O Channels and Processo* 261 7.8 External Interconne*ion Standards 263 7.9 IBM zEnterprise EC12 I/O Stru*ure 266 7. Key Terms, Review Questions, and Problems 270 Chapter.8 Oper*ing System Support 275 8.1 Oper*ing System Overview 276 8.2 Scheduling 287 8.3 Memory Management 293 8.4 Intel x86 Memory Management 304 8.5 Arm Memory Management 309 8.6 Key Terms, Review Questions, and Problems 314 PART THREE ARITHMETIC AND LOGIC 318 Chapter.9 Number Systems 318 9.1 The Deci*l System 319 9.2 Positional Number Systems 320 9.3 The Binary System 321 9.4 Converting Between Binary and Deci*l 321 9.5 Hexadeci*l Not*ion 324 9.6 Key Terms and Problems 326 Chapter. Computer Arit*etic 328 .1 The Arit*etic and Logic Unit.329 .2 Integer Represent*ion 330 .3 Integer Arit*etic 335 .4 Flo*ing-Point Represent*ion 350 .5 Flo*ing-Point Arit*etic 358 .6 Key Terms, Review Questions, and Problems 367 Chapter.11 Digital Logic 372 11.1 Boolean Algebra 373 11.2 G*es 376 11.3 Combin*ional Circuits 378 11.4 Sequential Circuits 396 11.5 Program*ble Logic Devices 405 11.6 Key Terms and Problems 409 PART FOUR THE CENTRAL PROCESSING UNIT.412 Chapter.12 Instru*ion Sets: Chara*eristics and Fun*ions 412 12.1 Machine Instru*ion Chara*eristics 413 12.2 Types of Operands 420 12.3 Intel x86 and ARM D*a Types 422 12.4 Types of Oper*ions 425 12.5 Intel x86 and ARM Oper*ion Types 438 12.6 Key Terms, Review Questions, and Problems 446 Appendix 12A Little-, Big-, and Bi-Endian 452 Chapter.13 Instru*ion Sets:Addressing Modes and For*ts 456 13.1 Addressing Modes 457 13.2 x86 and ARM Addressing Modes 463 13.3 Instru*ion For*ts 469 13.4 x86 and ARM Instru*ion For*ts 477 13.5 Assembly Language 482 13.6 Key Terms, Review Questions, and Problems 484 Chapter.14 Processor Stru*ure and Fun*ion 488 14.1 Processor Organiz*ion 489 14.2 Register Organiz*ion 491 14.3 Instru